1. Field of the Invention
The present invention relates to the field of DRAM device technology. More particularly, the present invention relates to a transistor device having a dielectric layer with multiple thicknesses and employed in a support circuit.
2. Description of the Prior Art
As known in the art, DRAM cells are typically operated under relatively high voltages. To maintain performance of the DRAM cells, the reliability of gate dielectric layer of the high-voltage MOS transistor devices disposed in the support circuit of the DRAM is very critical.
At present, to solve the troublesome boron penetration problem that typically occurs in a P+ gate MOS transistor device, a known decoupled plasma nitridation or DPN technique is employed to introduce nitrogen into the gate dielectric layer in the DRAM support circuit. However, the introduction of high concentration of nitrogen atoms in the gate dielectric layer of the high-voltage N+ gate MOS transistors deteriorates the reliability of the gate dielectric layer.
In light of the above, there is a strong need in this industry to provide a solution when facing the tradeoff between the performance of the P+ gate MOS transistor devices of the DRAM support circuit and the gate dielectric layer reliability of the high-voltage N+ gate MOS transistor devices.